The present invention relates to a PLL (Phase Lock Loop) circuit wherein the frequency drawing time and the frequency jitter are both reduced.
The PLL circuit is often used for preventing the clock skew in a system consisting of plural LSI (Large Scale Integrated) circuits.
In a LSI circuit, input signal is usually buffered and synchronized with a system clock at its input stage to be processed within its internal circuit, and the processed signal is also synchronized with the system clock at its output stage to be supplied through an output buffer to following LSI circuits. However, phase of the system clock supplied to output stage of an LSI circuit may differ to that supplied to input stages of its following LSI circuits, because of difference of delay times caused through system clock lines, that is, difference of numbers of buffers or load factors, for example, resulting in a clock skew disturbing correct data transfer.
The PLL circuit is used, in such a system, for driving all logic circuits, such as flip-flops consisting in counters, with the same timing, preventing the clock skew. Therefore, the frequency jitter of the PLL circuit used for preventing the clock skew should be strictly restricted, especially in a system having a high frequency system clock.
The PLL circuit is also used in digital audio equipment, such as CD (Compact Disk) players, DAT (Digital Audio Tape) players or BS (Broadcasting Satellite) tuners, wherein a clock signal is transfered together with digital audio data, according to a digital audio interface format, for re-generating the system clock by way of the PLL circuit, to be used for reproducing analog signals from the digital audio data.
Also in such a case, the PLL circuit with little jitter is required for reproducing high quality audio signals with accurate system clock.
FIG. 10 is a block diagram illustrating a PLL circuit disclosed for the purpose in a Japanese patent application laid open as a Provisional Publication No. 196715/'92.
Referring to FIG. 10, a PLL circuit according to this prior art comprises;
a phase comparator 11a for generating an up-down signal UD which becomes HIGH when a reference clock signal RCLK is phase advanced to an output clock signal CLK and vice versa, by comparing phases of the reference clock signal RCLK and the output clock signal CLK supplied thereto, PA1 a difference discrimination circuit 64 for generating a select signal SEL which indicates a slow count clock SCK when logic of the up-down signal UD alters, and indicates a fast count clock FCK when logic of the up-down signal UD remains at logic LOW or HIGH, PA1 a count clock selector 65 for selecting either the slow count clock SCK or the fast count clock FCK as a count clock CCLK according to the select signal SEL, PA1 an up-down counter 13a supplied with the up-down signal UD and the count clock CCLK for generating a count value COU which is incremented when the up-down signal UD is at logic HIGH while decremented when the up-down signal UD is at logic LOW, according to each pulse of the count clock CCLK, PA1 a D/A (Digital to Analog) converter 14 for outputting a control voltage VCT in proportion to the count value COU, and PA1 a VCO (Voltage Control Oscillator) 15 for providing the output clock signal CLK according to the control voltage VCT. PA1 a D/A converter for outputting a control voltage in proportion to the count value; and PA1 a VCO for providing the output clock signal according to the control voltage.
When the phase difference between the output clock signal CLK and the reference clock sign al RCLK is large, the phase comparator 11a maintains the up-down signal UD either at logic HIGH or at logic LOW, and so, the difference discrimination circuit 64 outputs the selection signal SEL so as to control the count clock selector 65 to select the fast count clock FCK. Therefore, the count value COU is incremented or decremented faster according to the fast count clock FCK than when the phase difference is minimum, where the up-down signal UD alters HIGH and LOW and the slow count clock SCK is selected and supplied to the up-down counter 13a as the count clock CCLK.
The output clock signal CLK, whereof frequency varies according to the control voltage VCT, namely, to the count value COU, is fed back to the phase comparator 11a, composing a feedback loop for automatically controlling the frequency and the phase of the output clock signal CLK.
FIG. 11 is a timing chart illustrating operation and the frequency drawing time, that is, a time necessary for the output clock signal CLK being phase-locked to the reference clock signal RCLK, of the PLL circuit of FIG. 10.
When the PLL circuit is initialized at a timing t.sub.i, the count value COU is set to '0000b' (binary value of four bits, assuming the up-down counter 13a is a four bit counter), and potential of the control voltage VCT output of the D/A converter 14 is lowest. Assuming the frequency of the reference clock signal RCLK is 100 MHz and frequency variable range of the VCO 15 is prepared to be .+-.10%, the VCO 15 outputs, therefore, the output clock signal CLK of about 9 to 10 MHz lower than the reference clock signal RCLK at the timing t.sub.i. So, the phase comparator 11a outputs the up-down signal UD at logic HIGH, which controls the up-down counter 13a to count up the count value COU at each pulse of the count clock CCLK, namely, the fast count clock FCK, as shown in FIG. 11, during the frequency drawing time ending at a timing t.sub.i, wherein phase of the output clock signal CLK is drawn, or advanced step by step towards that of the reference clock signal RCLK according to the fast count clock FCK.
When the frequency of the output clock signal CLK becomes higher than that of the reference clock signal RCLK and its phase becomes advanced to that of the reference clock signal RCLK at the timing t.sub.i, the up-down signal UD turns to LOW, which makes the count clock selector 65 select and output the slow count clock SCK. Therefore, the phase of the output clock signal CLK is locked near that of the reference clock signal RCLK, and the count value COU goes and returns between `1001b` and `1010b`, for example, making the frequency jitter of the output clock signal CLK.
As beforehand described, the frequency jitter should be strictly restricted to prevent the clock skew for the PLL circuit to be applied in a system having a high clock frequency.
For reducing the minimum jitter in the prior PLL circuit of FIG. 10, minimum discrimination level of the D/A converter 14 should be made more fine by enlarging bit width of the up-down counter 13a, or in other words, frequency variation of the VCO 15 for `0001b` of the count value COU should be reduced by increasing a maximum count number thereof, with the same frequency variable range of the VCO 15.
However, it results in another problem that the wider bit width of the up-down counter 13a makes the longer the frequency drawing time.
For example, assume that the frequency of the reference clock signal RCLK is 100 MHz, the bit width of the up-down counter 13a is four bits and the frequency variation of the VCO 15 is 1 MHz/bit.
In the case, the frequency of the output clock signal CLK varies from 100 MHz to 99 MHz, for example, when the count value COU decreases by `0001b`. Therefore, the minimum jitter becomes about 100 pS, that is, the difference between a cycle of 10.0 nS of 100 MHz and that of 10.1 nS of 99 MHz.
Using an up-down counter having a bit width of five bits, the minimum discrimination level of the D/A converter 14 can be made half and the minimum jitter can be reduced to 50 pS.
However, when the PLL circuit is prepared to be phase-locked at half of the maximum count value, it becomes `10000b` with the up-down counter of five bits, namely, two times of the count value of the up-down counter of four bits, needing two times of the frequency drawing time.
For the purpose to reduce the frequency drawing time by counting up quickly, the fast count clock FCK is prepared to be supplied to the up-down counter 13a, in the prior PLL circuit of FIG. 10.
However, there is also a frequency limit of the fast count clock FCK. When frequency of the count clock is too high, elements of the up-down counter, such as flip-flops, can not follow the clock pulse, resulting in a malfunction of the up-down counter. For example, the frequency limit of the fast count clock FCK becomes about 100 MHz when the setup time of the flip-flops is about 2 nS, which makes the operation cycle of the up-down counter 13a about 8 nS.